1. Technical Field
The present invention relates in general to a method and apparatus for managing write-to-read turnarounds in an early read after write (ERAW) memory system. More particularly, the present invention relates to a method and apparatus for issuing a write operation to a DRAM bank set and subsequently issuing an early read operation to a different DRAM bank set based upon a different bank set write-to-read timing parameter.
2. Description of the Related Art
Computer system developers constantly strive to increase a computer system's performance. The developers may focus on optimizing software components and/or hardware components in order to achieve this goal. One hardware optimization approach is to improve a processor's rate of reading from memory and writing to memory.
Hardware developers have designed a dynamic random access memory (DRAM) interface that includes a high-speed chip-to-chip data transfer technology. The interface technology may be implemented on standard CMOS DRAM cores and CMOS controller chips for applications such as high-performance main memory, PC graphics, game consoles, advanced digital consumer systems, high-performance networking systems, and other demanding applications requiring high-bandwidth memory subsystems.
DRAMs may include an “even” bank set and an “odd” bank set, whereby memory read operations and memory write operations correspond to a particular bank set. An early read after write feature of particular DRAMs, such as extreme data rate (XDR™) DRAMs, allows a read operation targeted to one bank set to commence before the completion of a write operation that was issued to a different bank set. For example, if an even bank write operation executes, an odd bank read operation may start before the even bank write operation completes. The time between the start of the write operation and the start of a different bank set read operation may be referred to as the “different bank set write-to-read turnaround time.” Likewise, the time between the start of a write operation and the start of a same bank set read operation may be referred to as the “same bank set write-to-read turnaround time.”
A challenge found with existing art, however, is since the different bank set write-to-read turnaround time is not the same time as the same bank set write-to-read turnaround time, it is difficult to manage these two timing parameters in order to achieve optimal memory system performance. Another challenge found is having the operation arbitration in the memory controller select the best type of read operation whenever possible, such as one that corresponds to a different bank set. If a memory system waits to send a different bank set read operation based upon the same bank set write-to-read turnaround time, system performance is degraded. And, if a memory system sends a same bank set read operation based upon the different bank set write-to-read turnaround time, bus conflicts arise.
What is needed, therefore, is a method and apparatus to manage same bank set write-to-read turnaround times and different bank set write-to-read turnaround times in order to optimize memory system performance in an early read after write memory system.